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<div class="title">xclk_wiz_hw.h File Reference</div>  </div>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gaa454fd2cfc7ed730c52b747b72de71ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaa454fd2cfc7ed730c52b747b72de71ef">XCLK_WIZ_IER_ALLINTR_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gaa454fd2cfc7ed730c52b747b72de71ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupts enable mask.  <a href="group__clk__wiz__v1__0.html#gaa454fd2cfc7ed730c52b747b72de71ef">More...</a><br /></td></tr>
<tr class="separator:gaa454fd2cfc7ed730c52b747b72de71ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18e65431f48acae3734420b5f3ffa490"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga18e65431f48acae3734420b5f3ffa490">XCLK_WIZ_IER_ALLINTR_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga18e65431f48acae3734420b5f3ffa490"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupts enable shift bits.  <a href="group__clk__wiz__v1__0.html#ga18e65431f48acae3734420b5f3ffa490">More...</a><br /></td></tr>
<tr class="separator:ga18e65431f48acae3734420b5f3ffa490"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e1db287d69d02c673140eae664c1a34"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga8e1db287d69d02c673140eae664c1a34">XCLK_WIZ_ISR_ALLINTR_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga8e1db287d69d02c673140eae664c1a34"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupt status register mask.  <a href="group__clk__wiz__v1__0.html#ga8e1db287d69d02c673140eae664c1a34">More...</a><br /></td></tr>
<tr class="separator:ga8e1db287d69d02c673140eae664c1a34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga757264554263d3e4035a7433e43ade17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga757264554263d3e4035a7433e43ade17">XCLK_WIZ_ISR_ALLINTR_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga757264554263d3e4035a7433e43ade17"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupts status register shift.  <a href="group__clk__wiz__v1__0.html#ga757264554263d3e4035a7433e43ade17">More...</a><br /></td></tr>
<tr class="separator:ga757264554263d3e4035a7433e43ade17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register sets of CLK_WIZ </p>
</div></td></tr>
<tr class="memitem:ga54bfc49d1a188b798cb96cfd40a0dc54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga54bfc49d1a188b798cb96cfd40a0dc54">XCLK_WIZ_ISR_OFFSET</a>&#160;&#160;&#160;0x0000000C</td></tr>
<tr class="memdesc:ga54bfc49d1a188b798cb96cfd40a0dc54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="group__clk__wiz__v1__0.html#ga54bfc49d1a188b798cb96cfd40a0dc54">More...</a><br /></td></tr>
<tr class="separator:ga54bfc49d1a188b798cb96cfd40a0dc54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab5f77647fad82a4c02eb29b8180f89b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaab5f77647fad82a4c02eb29b8180f89b">XCLK_WIZ_IER_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gaab5f77647fad82a4c02eb29b8180f89b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Register.  <a href="group__clk__wiz__v1__0.html#gaab5f77647fad82a4c02eb29b8180f89b">More...</a><br /></td></tr>
<tr class="separator:gaab5f77647fad82a4c02eb29b8180f89b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XCLK_WIZ_ISR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to display interrupt status register </p>
</div></td></tr>
<tr class="memitem:ga6a11cf2b70a1598342cde6ad50577ec9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga6a11cf2b70a1598342cde6ad50577ec9">XCLK_WIZ_ISR_CLK3_STOP_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:ga6a11cf2b70a1598342cde6ad50577ec9"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 3 stopped.  <a href="group__clk__wiz__v1__0.html#ga6a11cf2b70a1598342cde6ad50577ec9">More...</a><br /></td></tr>
<tr class="separator:ga6a11cf2b70a1598342cde6ad50577ec9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab7ecb70f6cf41fd44769722fdcf2a6a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gab7ecb70f6cf41fd44769722fdcf2a6a6">XCLK_WIZ_ISR_CLK2_STOP_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:gab7ecb70f6cf41fd44769722fdcf2a6a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 2 stopped.  <a href="group__clk__wiz__v1__0.html#gab7ecb70f6cf41fd44769722fdcf2a6a6">More...</a><br /></td></tr>
<tr class="separator:gab7ecb70f6cf41fd44769722fdcf2a6a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7152a10657a3caeef169c0be28087362"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga7152a10657a3caeef169c0be28087362">XCLK_WIZ_ISR_CLK1_STOP_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:ga7152a10657a3caeef169c0be28087362"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 1 stopped.  <a href="group__clk__wiz__v1__0.html#ga7152a10657a3caeef169c0be28087362">More...</a><br /></td></tr>
<tr class="separator:ga7152a10657a3caeef169c0be28087362"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29f231a7715e94baec2277b768f5f1a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga29f231a7715e94baec2277b768f5f1a5">XCLK_WIZ_ISR_CLK0_STOP_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:ga29f231a7715e94baec2277b768f5f1a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 0 stopped.  <a href="group__clk__wiz__v1__0.html#ga29f231a7715e94baec2277b768f5f1a5">More...</a><br /></td></tr>
<tr class="separator:ga29f231a7715e94baec2277b768f5f1a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5634a366b8ced209061e028c163fddd5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga5634a366b8ced209061e028c163fddd5">XCLK_WIZ_ISR_CLK3_GLITCH_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga5634a366b8ced209061e028c163fddd5"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 3 has glitch.  <a href="group__clk__wiz__v1__0.html#ga5634a366b8ced209061e028c163fddd5">More...</a><br /></td></tr>
<tr class="separator:ga5634a366b8ced209061e028c163fddd5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa79abe7629e383c5d83f09ab640a7267"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaa79abe7629e383c5d83f09ab640a7267">XCLK_WIZ_ISR_CLK2_GLITCH_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:gaa79abe7629e383c5d83f09ab640a7267"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 2 has glitch.  <a href="group__clk__wiz__v1__0.html#gaa79abe7629e383c5d83f09ab640a7267">More...</a><br /></td></tr>
<tr class="separator:gaa79abe7629e383c5d83f09ab640a7267"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafcb540ab2c83a559450ae71633258269"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gafcb540ab2c83a559450ae71633258269">XCLK_WIZ_ISR_CLK1_GLITCH_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:gafcb540ab2c83a559450ae71633258269"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 1 has glitch.  <a href="group__clk__wiz__v1__0.html#gafcb540ab2c83a559450ae71633258269">More...</a><br /></td></tr>
<tr class="separator:gafcb540ab2c83a559450ae71633258269"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf7f48abd562e1b1389b86bb978f091e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gabf7f48abd562e1b1389b86bb978f091e">XCLK_WIZ_ISR_CLK0_GLITCH_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gabf7f48abd562e1b1389b86bb978f091e"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 0 has glitch.  <a href="group__clk__wiz__v1__0.html#gabf7f48abd562e1b1389b86bb978f091e">More...</a><br /></td></tr>
<tr class="separator:gabf7f48abd562e1b1389b86bb978f091e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga163b2686ce7e37b98fc9d510a95febdb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga163b2686ce7e37b98fc9d510a95febdb">XCLK_WIZ_ISR_CLK3_MINFREQ_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga163b2686ce7e37b98fc9d510a95febdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 3 is less than specification.  <a href="group__clk__wiz__v1__0.html#ga163b2686ce7e37b98fc9d510a95febdb">More...</a><br /></td></tr>
<tr class="separator:ga163b2686ce7e37b98fc9d510a95febdb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga24b899afdcc87e9a2c97eabe52fb610c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga24b899afdcc87e9a2c97eabe52fb610c">XCLK_WIZ_ISR_CLK2_MINFREQ_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga24b899afdcc87e9a2c97eabe52fb610c"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 2 is less than specification.  <a href="group__clk__wiz__v1__0.html#ga24b899afdcc87e9a2c97eabe52fb610c">More...</a><br /></td></tr>
<tr class="separator:ga24b899afdcc87e9a2c97eabe52fb610c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e3dd7df0cf46c203cab6d190c9e4cd9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga8e3dd7df0cf46c203cab6d190c9e4cd9">XCLK_WIZ_ISR_CLK1_MINFREQ_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga8e3dd7df0cf46c203cab6d190c9e4cd9"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 1 is less than specification.  <a href="group__clk__wiz__v1__0.html#ga8e3dd7df0cf46c203cab6d190c9e4cd9">More...</a><br /></td></tr>
<tr class="separator:ga8e3dd7df0cf46c203cab6d190c9e4cd9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga37ecc718da5a33c16329f6f6d1967e4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga37ecc718da5a33c16329f6f6d1967e4e">XCLK_WIZ_ISR_CLK0_MINFREQ_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga37ecc718da5a33c16329f6f6d1967e4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 0 is less than specification.  <a href="group__clk__wiz__v1__0.html#ga37ecc718da5a33c16329f6f6d1967e4e">More...</a><br /></td></tr>
<tr class="separator:ga37ecc718da5a33c16329f6f6d1967e4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a3354cec0d629d0ed3c26d28bbd1994"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga9a3354cec0d629d0ed3c26d28bbd1994">XCLK_WIZ_ISR_CLK3_MAXFREQ_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga9a3354cec0d629d0ed3c26d28bbd1994"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 3 is max than specification.  <a href="group__clk__wiz__v1__0.html#ga9a3354cec0d629d0ed3c26d28bbd1994">More...</a><br /></td></tr>
<tr class="separator:ga9a3354cec0d629d0ed3c26d28bbd1994"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2cfaf083bfc11e4d527262c6dfe0c24e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga2cfaf083bfc11e4d527262c6dfe0c24e">XCLK_WIZ_ISR_CLK2_MAXFREQ_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga2cfaf083bfc11e4d527262c6dfe0c24e"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 2 is max than specification.  <a href="group__clk__wiz__v1__0.html#ga2cfaf083bfc11e4d527262c6dfe0c24e">More...</a><br /></td></tr>
<tr class="separator:ga2cfaf083bfc11e4d527262c6dfe0c24e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga834ed8f9541edc0c5be94ca0de404f87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga834ed8f9541edc0c5be94ca0de404f87">XCLK_WIZ_ISR_CLK1_MAXFREQ_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga834ed8f9541edc0c5be94ca0de404f87"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 1 is max than specification.  <a href="group__clk__wiz__v1__0.html#ga834ed8f9541edc0c5be94ca0de404f87">More...</a><br /></td></tr>
<tr class="separator:ga834ed8f9541edc0c5be94ca0de404f87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e762fe87dddbe8ac453306748a216f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga5e762fe87dddbe8ac453306748a216f5">XCLK_WIZ_ISR_CLK0_MAXFREQ_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga5e762fe87dddbe8ac453306748a216f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 0 is max than specification.  <a href="group__clk__wiz__v1__0.html#ga5e762fe87dddbe8ac453306748a216f5">More...</a><br /></td></tr>
<tr class="separator:ga5e762fe87dddbe8ac453306748a216f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga82daa29abf414a316c26355e3771cf88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga82daa29abf414a316c26355e3771cf88">XCLK_WIZ_ISR_CLKALL_STOP_MASK</a>&#160;&#160;&#160;0x0000F000</td></tr>
<tr class="memdesc:ga82daa29abf414a316c26355e3771cf88"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock[0-3] has stopped.  <a href="group__clk__wiz__v1__0.html#ga82daa29abf414a316c26355e3771cf88">More...</a><br /></td></tr>
<tr class="separator:ga82daa29abf414a316c26355e3771cf88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga868aa5dd6399404298d686e73a44a565"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga868aa5dd6399404298d686e73a44a565">XCLK_WIZ_ISR_CLKALL_GLITCH_MASK</a>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="memdesc:ga868aa5dd6399404298d686e73a44a565"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock[0-3] has glitch.  <a href="group__clk__wiz__v1__0.html#ga868aa5dd6399404298d686e73a44a565">More...</a><br /></td></tr>
<tr class="separator:ga868aa5dd6399404298d686e73a44a565"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9cfc8a66cb70f62b8546fb4b9a448d50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga9cfc8a66cb70f62b8546fb4b9a448d50">XCLK_WIZ_ISR_CLKALL_MINFREQ_MASK</a>&#160;&#160;&#160;0x000000F0</td></tr>
<tr class="memdesc:ga9cfc8a66cb70f62b8546fb4b9a448d50"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock[0-3] is min than specification.  <a href="group__clk__wiz__v1__0.html#ga9cfc8a66cb70f62b8546fb4b9a448d50">More...</a><br /></td></tr>
<tr class="separator:ga9cfc8a66cb70f62b8546fb4b9a448d50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b6a6f0f1fda56cdb7b97a293e9ee72e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga7b6a6f0f1fda56cdb7b97a293e9ee72e">XCLK_WIZ_ISR_CLKALL_MAXFREQ_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:ga7b6a6f0f1fda56cdb7b97a293e9ee72e"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock[0-3] is max than specification.  <a href="group__clk__wiz__v1__0.html#ga7b6a6f0f1fda56cdb7b97a293e9ee72e">More...</a><br /></td></tr>
<tr class="separator:ga7b6a6f0f1fda56cdb7b97a293e9ee72e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga546bf7c1903e83e52e69fbaa1d603343"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga546bf7c1903e83e52e69fbaa1d603343">XCLK_WIZ_ISR_CLK3_STOP_SHIFT</a>&#160;&#160;&#160;15</td></tr>
<tr class="memdesc:ga546bf7c1903e83e52e69fbaa1d603343"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 3 stop.  <a href="group__clk__wiz__v1__0.html#ga546bf7c1903e83e52e69fbaa1d603343">More...</a><br /></td></tr>
<tr class="separator:ga546bf7c1903e83e52e69fbaa1d603343"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3a0cc16b3ad77228b11f05e11d6e733"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaf3a0cc16b3ad77228b11f05e11d6e733">XCLK_WIZ_ISR_CLK2_STOP_SHIFT</a>&#160;&#160;&#160;14</td></tr>
<tr class="memdesc:gaf3a0cc16b3ad77228b11f05e11d6e733"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 2 stop.  <a href="group__clk__wiz__v1__0.html#gaf3a0cc16b3ad77228b11f05e11d6e733">More...</a><br /></td></tr>
<tr class="separator:gaf3a0cc16b3ad77228b11f05e11d6e733"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab79b4b574363916c1021f811376f1660"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gab79b4b574363916c1021f811376f1660">XCLK_WIZ_ISR_CLK1_STOP_SHIFT</a>&#160;&#160;&#160;13</td></tr>
<tr class="memdesc:gab79b4b574363916c1021f811376f1660"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 1 stop.  <a href="group__clk__wiz__v1__0.html#gab79b4b574363916c1021f811376f1660">More...</a><br /></td></tr>
<tr class="separator:gab79b4b574363916c1021f811376f1660"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0f168b5c26d91d8aa5c92d7a4e922631"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga0f168b5c26d91d8aa5c92d7a4e922631">XCLK_WIZ_ISR_CLK0_STOP_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:ga0f168b5c26d91d8aa5c92d7a4e922631"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 0 stop.  <a href="group__clk__wiz__v1__0.html#ga0f168b5c26d91d8aa5c92d7a4e922631">More...</a><br /></td></tr>
<tr class="separator:ga0f168b5c26d91d8aa5c92d7a4e922631"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0914e2de55970b885f8c50667b85c8f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga0914e2de55970b885f8c50667b85c8f3">XCLK_WIZ_ISR_CLK3_GLITCH_SHIFT</a>&#160;&#160;&#160;11</td></tr>
<tr class="memdesc:ga0914e2de55970b885f8c50667b85c8f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 3 glitch.  <a href="group__clk__wiz__v1__0.html#ga0914e2de55970b885f8c50667b85c8f3">More...</a><br /></td></tr>
<tr class="separator:ga0914e2de55970b885f8c50667b85c8f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac893b3b69a6950f520de28c97b80f149"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gac893b3b69a6950f520de28c97b80f149">XCLK_WIZ_ISR_CLK2_GLITCH_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:gac893b3b69a6950f520de28c97b80f149"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 2 glitch.  <a href="group__clk__wiz__v1__0.html#gac893b3b69a6950f520de28c97b80f149">More...</a><br /></td></tr>
<tr class="separator:gac893b3b69a6950f520de28c97b80f149"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6cd50be9be9ce6dda280b3200d73c236"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga6cd50be9be9ce6dda280b3200d73c236">XCLK_WIZ_ISR_CLK1_GLITCH_SHIFT</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:ga6cd50be9be9ce6dda280b3200d73c236"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 1 glitch.  <a href="group__clk__wiz__v1__0.html#ga6cd50be9be9ce6dda280b3200d73c236">More...</a><br /></td></tr>
<tr class="separator:ga6cd50be9be9ce6dda280b3200d73c236"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa28febc03c84cdbbffc5ea57e4124fe7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaa28febc03c84cdbbffc5ea57e4124fe7">XCLK_WIZ_ISR_CLK0_GLITCH_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gaa28febc03c84cdbbffc5ea57e4124fe7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 0 glitch.  <a href="group__clk__wiz__v1__0.html#gaa28febc03c84cdbbffc5ea57e4124fe7">More...</a><br /></td></tr>
<tr class="separator:gaa28febc03c84cdbbffc5ea57e4124fe7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf702d2921c3b616066cfd2e76de620b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaf702d2921c3b616066cfd2e76de620b2">XCLK_WIZ_ISR_CLK3_MINFREQ_SHIFT</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:gaf702d2921c3b616066cfd2e76de620b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 3 less.  <a href="group__clk__wiz__v1__0.html#gaf702d2921c3b616066cfd2e76de620b2">More...</a><br /></td></tr>
<tr class="separator:gaf702d2921c3b616066cfd2e76de620b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d719247c9dfed11e36dfacb58f25fb8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga4d719247c9dfed11e36dfacb58f25fb8">XCLK_WIZ_ISR_CLK2_MINFREQ_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga4d719247c9dfed11e36dfacb58f25fb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 2 less.  <a href="group__clk__wiz__v1__0.html#ga4d719247c9dfed11e36dfacb58f25fb8">More...</a><br /></td></tr>
<tr class="separator:ga4d719247c9dfed11e36dfacb58f25fb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4ffc8a12873db9cdcb8e31c9bfdf923"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gad4ffc8a12873db9cdcb8e31c9bfdf923">XCLK_WIZ_ISR_CLK1_MINFREQ_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:gad4ffc8a12873db9cdcb8e31c9bfdf923"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 1 less.  <a href="group__clk__wiz__v1__0.html#gad4ffc8a12873db9cdcb8e31c9bfdf923">More...</a><br /></td></tr>
<tr class="separator:gad4ffc8a12873db9cdcb8e31c9bfdf923"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga737f9a73cb6f0fe8402585a70f35492c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga737f9a73cb6f0fe8402585a70f35492c">XCLK_WIZ_ISR_CLK0_MINFREQ_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga737f9a73cb6f0fe8402585a70f35492c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 0 less.  <a href="group__clk__wiz__v1__0.html#ga737f9a73cb6f0fe8402585a70f35492c">More...</a><br /></td></tr>
<tr class="separator:ga737f9a73cb6f0fe8402585a70f35492c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f70d46d84d4629688388134ebc3dca6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga5f70d46d84d4629688388134ebc3dca6">XCLK_WIZ_ISR_CLK3_MAXFREQ_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga5f70d46d84d4629688388134ebc3dca6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 3 max.  <a href="group__clk__wiz__v1__0.html#ga5f70d46d84d4629688388134ebc3dca6">More...</a><br /></td></tr>
<tr class="separator:ga5f70d46d84d4629688388134ebc3dca6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac546d9f62ddcc7fc8584ef9de13d7bb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gac546d9f62ddcc7fc8584ef9de13d7bb9">XCLK_WIZ_ISR_CLK2_MAXFREQ_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:gac546d9f62ddcc7fc8584ef9de13d7bb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 2 max.  <a href="group__clk__wiz__v1__0.html#gac546d9f62ddcc7fc8584ef9de13d7bb9">More...</a><br /></td></tr>
<tr class="separator:gac546d9f62ddcc7fc8584ef9de13d7bb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga176e2701427376ad264054f9abd3f1ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga176e2701427376ad264054f9abd3f1ba">XCLK_WIZ_ISR_CLK1_MAXFREQ_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga176e2701427376ad264054f9abd3f1ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 1 max.  <a href="group__clk__wiz__v1__0.html#ga176e2701427376ad264054f9abd3f1ba">More...</a><br /></td></tr>
<tr class="separator:ga176e2701427376ad264054f9abd3f1ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga991df75896a6505b7d17031df5216319"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga991df75896a6505b7d17031df5216319">XCLK_WIZ_ISR_CLK0_MAXFREQ_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga991df75896a6505b7d17031df5216319"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 0 max.  <a href="group__clk__wiz__v1__0.html#ga991df75896a6505b7d17031df5216319">More...</a><br /></td></tr>
<tr class="separator:ga991df75896a6505b7d17031df5216319"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XCLK_WIZ_IER_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to display interrupt status register </p>
</div></td></tr>
<tr class="memitem:gaa19f2cd1e19eefbe675b2ca7433a6594"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaa19f2cd1e19eefbe675b2ca7433a6594">XCLK_WIZ_IER_CLK3_STOP_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:gaa19f2cd1e19eefbe675b2ca7433a6594"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 3 stopped.  <a href="group__clk__wiz__v1__0.html#gaa19f2cd1e19eefbe675b2ca7433a6594">More...</a><br /></td></tr>
<tr class="separator:gaa19f2cd1e19eefbe675b2ca7433a6594"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa29a0866b87ef2332a9e8076676e4e11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaa29a0866b87ef2332a9e8076676e4e11">XCLK_WIZ_IER_CLK2_STOP_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:gaa29a0866b87ef2332a9e8076676e4e11"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 2 stopped.  <a href="group__clk__wiz__v1__0.html#gaa29a0866b87ef2332a9e8076676e4e11">More...</a><br /></td></tr>
<tr class="separator:gaa29a0866b87ef2332a9e8076676e4e11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaea0e4748f55d38744ca6f95ccd68a1ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaea0e4748f55d38744ca6f95ccd68a1ad">XCLK_WIZ_IER_CLK1_STOP_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:gaea0e4748f55d38744ca6f95ccd68a1ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 1 stopped.  <a href="group__clk__wiz__v1__0.html#gaea0e4748f55d38744ca6f95ccd68a1ad">More...</a><br /></td></tr>
<tr class="separator:gaea0e4748f55d38744ca6f95ccd68a1ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac73712dd09ff0df8c1d71a53e4c826ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gac73712dd09ff0df8c1d71a53e4c826ce">XCLK_WIZ_IER_CLK0_STOP_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:gac73712dd09ff0df8c1d71a53e4c826ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 0 stopped.  <a href="group__clk__wiz__v1__0.html#gac73712dd09ff0df8c1d71a53e4c826ce">More...</a><br /></td></tr>
<tr class="separator:gac73712dd09ff0df8c1d71a53e4c826ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0df64f19a3ed2d4a49889b9ca8bfbb3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga0df64f19a3ed2d4a49889b9ca8bfbb3a">XCLK_WIZ_IER_CLK3_GLITCH_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga0df64f19a3ed2d4a49889b9ca8bfbb3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 3 has glitch.  <a href="group__clk__wiz__v1__0.html#ga0df64f19a3ed2d4a49889b9ca8bfbb3a">More...</a><br /></td></tr>
<tr class="separator:ga0df64f19a3ed2d4a49889b9ca8bfbb3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a23825d334858f643dd8bdeeac557c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga0a23825d334858f643dd8bdeeac557c8">XCLK_WIZ_IER_CLK2_GLITCH_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga0a23825d334858f643dd8bdeeac557c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 2 has glitch.  <a href="group__clk__wiz__v1__0.html#ga0a23825d334858f643dd8bdeeac557c8">More...</a><br /></td></tr>
<tr class="separator:ga0a23825d334858f643dd8bdeeac557c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb022733e8a876fee569991cb5c548f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gabb022733e8a876fee569991cb5c548f3">XCLK_WIZ_IER_CLK1_GLITCH_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:gabb022733e8a876fee569991cb5c548f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 1 has glitch.  <a href="group__clk__wiz__v1__0.html#gabb022733e8a876fee569991cb5c548f3">More...</a><br /></td></tr>
<tr class="separator:gabb022733e8a876fee569991cb5c548f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f63ddcc1041b05a1da8790ce88064b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga1f63ddcc1041b05a1da8790ce88064b2">XCLK_WIZ_IER_CLK0_GLITCH_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga1f63ddcc1041b05a1da8790ce88064b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 0 has glitch.  <a href="group__clk__wiz__v1__0.html#ga1f63ddcc1041b05a1da8790ce88064b2">More...</a><br /></td></tr>
<tr class="separator:ga1f63ddcc1041b05a1da8790ce88064b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8ed2bdc3136a5a915c0ff8902c93e6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gab8ed2bdc3136a5a915c0ff8902c93e6f">XCLK_WIZ_IER_CLK3_MINFREQ_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gab8ed2bdc3136a5a915c0ff8902c93e6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 3 is less than specification.  <a href="group__clk__wiz__v1__0.html#gab8ed2bdc3136a5a915c0ff8902c93e6f">More...</a><br /></td></tr>
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<tr class="memitem:gabe0932d7fe457fcf7530e782de0b1b08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gabe0932d7fe457fcf7530e782de0b1b08">XCLK_WIZ_IER_CLK2_MINFREQ_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gabe0932d7fe457fcf7530e782de0b1b08"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 2 is less than specification.  <a href="group__clk__wiz__v1__0.html#gabe0932d7fe457fcf7530e782de0b1b08">More...</a><br /></td></tr>
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<tr class="memitem:ga057dc5e6b87b7ba9333ec0e44ac40c9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga057dc5e6b87b7ba9333ec0e44ac40c9a">XCLK_WIZ_IER_CLK1_MINFREQ_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga057dc5e6b87b7ba9333ec0e44ac40c9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 1 is less than specification.  <a href="group__clk__wiz__v1__0.html#ga057dc5e6b87b7ba9333ec0e44ac40c9a">More...</a><br /></td></tr>
<tr class="separator:ga057dc5e6b87b7ba9333ec0e44ac40c9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga125707922533b9049f08dd26271519d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga125707922533b9049f08dd26271519d5">XCLK_WIZ_IER_CLK0_MINFREQ_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga125707922533b9049f08dd26271519d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 0 is less than specification.  <a href="group__clk__wiz__v1__0.html#ga125707922533b9049f08dd26271519d5">More...</a><br /></td></tr>
<tr class="separator:ga125707922533b9049f08dd26271519d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga32f362272205283dba350e23e7222a3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga32f362272205283dba350e23e7222a3a">XCLK_WIZ_IER_CLK3_MAXFREQ_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga32f362272205283dba350e23e7222a3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 3 is max than specification.  <a href="group__clk__wiz__v1__0.html#ga32f362272205283dba350e23e7222a3a">More...</a><br /></td></tr>
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<tr class="memitem:ga0e663b1df0fb873cbbe96967b980426b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga0e663b1df0fb873cbbe96967b980426b">XCLK_WIZ_IER_CLK2_MAXFREQ_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga0e663b1df0fb873cbbe96967b980426b"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 2 is max than specification.  <a href="group__clk__wiz__v1__0.html#ga0e663b1df0fb873cbbe96967b980426b">More...</a><br /></td></tr>
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<tr class="memitem:ga8c45e5d3fad76bf173750242c885e3d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga8c45e5d3fad76bf173750242c885e3d4">XCLK_WIZ_IER_CLK1_MAXFREQ_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga8c45e5d3fad76bf173750242c885e3d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 1 is max than specification.  <a href="group__clk__wiz__v1__0.html#ga8c45e5d3fad76bf173750242c885e3d4">More...</a><br /></td></tr>
<tr class="separator:ga8c45e5d3fad76bf173750242c885e3d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0119267bfa918f08ca0a11de0951b2ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga0119267bfa918f08ca0a11de0951b2ab">XCLK_WIZ_IER_CLK0_MAXFREQ_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga0119267bfa918f08ca0a11de0951b2ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">User clock 0 is max than specification.  <a href="group__clk__wiz__v1__0.html#ga0119267bfa918f08ca0a11de0951b2ab">More...</a><br /></td></tr>
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<tr class="memitem:ga7bb1dd7a981035a3aa91248e00ae98ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga7bb1dd7a981035a3aa91248e00ae98ad">XCLK_WIZ_IER_CLK3_STOP_SHIFT</a>&#160;&#160;&#160;15</td></tr>
<tr class="memdesc:ga7bb1dd7a981035a3aa91248e00ae98ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 3 stop.  <a href="group__clk__wiz__v1__0.html#ga7bb1dd7a981035a3aa91248e00ae98ad">More...</a><br /></td></tr>
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<tr class="memitem:gafbb37482481fd93ec9ab5253a0796fd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gafbb37482481fd93ec9ab5253a0796fd7">XCLK_WIZ_IER_CLK2_STOP_SHIFT</a>&#160;&#160;&#160;14</td></tr>
<tr class="memdesc:gafbb37482481fd93ec9ab5253a0796fd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 2 stop.  <a href="group__clk__wiz__v1__0.html#gafbb37482481fd93ec9ab5253a0796fd7">More...</a><br /></td></tr>
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<tr class="memitem:ga44438e619f42b96ccc021a1c3063f6b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga44438e619f42b96ccc021a1c3063f6b8">XCLK_WIZ_IER_CLK1_STOP_SHIFT</a>&#160;&#160;&#160;13</td></tr>
<tr class="memdesc:ga44438e619f42b96ccc021a1c3063f6b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 1 stop.  <a href="group__clk__wiz__v1__0.html#ga44438e619f42b96ccc021a1c3063f6b8">More...</a><br /></td></tr>
<tr class="separator:ga44438e619f42b96ccc021a1c3063f6b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2872e30e84d68905c43bd7806cc83fa0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga2872e30e84d68905c43bd7806cc83fa0">XCLK_WIZ_IER_CLK0_STOP_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:ga2872e30e84d68905c43bd7806cc83fa0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 0 stop.  <a href="group__clk__wiz__v1__0.html#ga2872e30e84d68905c43bd7806cc83fa0">More...</a><br /></td></tr>
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<tr class="memitem:ga1ca586bbfdafb1acb2ce1fd97a4902b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga1ca586bbfdafb1acb2ce1fd97a4902b1">XCLK_WIZ_IER_CLK3_GLITCH_SHIFT</a>&#160;&#160;&#160;11</td></tr>
<tr class="memdesc:ga1ca586bbfdafb1acb2ce1fd97a4902b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 3 glitch.  <a href="group__clk__wiz__v1__0.html#ga1ca586bbfdafb1acb2ce1fd97a4902b1">More...</a><br /></td></tr>
<tr class="separator:ga1ca586bbfdafb1acb2ce1fd97a4902b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaac99c7c36e58c2177e35f81ea3ce1c60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gaac99c7c36e58c2177e35f81ea3ce1c60">XCLK_WIZ_IER_CLK2_GLITCH_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:gaac99c7c36e58c2177e35f81ea3ce1c60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 2 glitch.  <a href="group__clk__wiz__v1__0.html#gaac99c7c36e58c2177e35f81ea3ce1c60">More...</a><br /></td></tr>
<tr class="separator:gaac99c7c36e58c2177e35f81ea3ce1c60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga19877011447febc4438bc39978270229"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga19877011447febc4438bc39978270229">XCLK_WIZ_IER_CLK1_GLITCH_SHIFT</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:ga19877011447febc4438bc39978270229"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 1 glitch.  <a href="group__clk__wiz__v1__0.html#ga19877011447febc4438bc39978270229">More...</a><br /></td></tr>
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<tr class="memitem:gad55c9367027a06417ae89436f7ba3b77"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gad55c9367027a06417ae89436f7ba3b77">XCLK_WIZ_IER_CLK0_GLITCH_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gad55c9367027a06417ae89436f7ba3b77"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 0 glitch.  <a href="group__clk__wiz__v1__0.html#gad55c9367027a06417ae89436f7ba3b77">More...</a><br /></td></tr>
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<tr class="memitem:ga2073518a02f6716b33fd721eed2740b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga2073518a02f6716b33fd721eed2740b5">XCLK_WIZ_IER_CLK3_MINFREQ_SHIFT</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:ga2073518a02f6716b33fd721eed2740b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 3 less.  <a href="group__clk__wiz__v1__0.html#ga2073518a02f6716b33fd721eed2740b5">More...</a><br /></td></tr>
<tr class="separator:ga2073518a02f6716b33fd721eed2740b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d7b6317ea1bc997bac64ff903f253b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga9d7b6317ea1bc997bac64ff903f253b8">XCLK_WIZ_IER_CLK2_MINFREQ_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga9d7b6317ea1bc997bac64ff903f253b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 2 less.  <a href="group__clk__wiz__v1__0.html#ga9d7b6317ea1bc997bac64ff903f253b8">More...</a><br /></td></tr>
<tr class="separator:ga9d7b6317ea1bc997bac64ff903f253b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e862f52dce0734899a9b851b0b59b7e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga8e862f52dce0734899a9b851b0b59b7e">XCLK_WIZ_IER_CLK1_MINFREQ_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga8e862f52dce0734899a9b851b0b59b7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 1 less.  <a href="group__clk__wiz__v1__0.html#ga8e862f52dce0734899a9b851b0b59b7e">More...</a><br /></td></tr>
<tr class="separator:ga8e862f52dce0734899a9b851b0b59b7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9429606a7f041a1c7995a01b3b16c83f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga9429606a7f041a1c7995a01b3b16c83f">XCLK_WIZ_IER_CLK0_MINFREQ_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga9429606a7f041a1c7995a01b3b16c83f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 0 less.  <a href="group__clk__wiz__v1__0.html#ga9429606a7f041a1c7995a01b3b16c83f">More...</a><br /></td></tr>
<tr class="separator:ga9429606a7f041a1c7995a01b3b16c83f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5528da0dd2acef0622e92b42cde63b30"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga5528da0dd2acef0622e92b42cde63b30">XCLK_WIZ_IER_CLK3_MAXFREQ_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga5528da0dd2acef0622e92b42cde63b30"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 3 max.  <a href="group__clk__wiz__v1__0.html#ga5528da0dd2acef0622e92b42cde63b30">More...</a><br /></td></tr>
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<tr class="memitem:gabb60b1ae1eb59840446df19b84379396"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gabb60b1ae1eb59840446df19b84379396">XCLK_WIZ_IER_CLK2_MAXFREQ_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:gabb60b1ae1eb59840446df19b84379396"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 2 max.  <a href="group__clk__wiz__v1__0.html#gabb60b1ae1eb59840446df19b84379396">More...</a><br /></td></tr>
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<tr class="memitem:gab9224e9f271c5ab6f75811dc297c10db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#gab9224e9f271c5ab6f75811dc297c10db">XCLK_WIZ_IER_CLK1_MAXFREQ_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gab9224e9f271c5ab6f75811dc297c10db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 1 max.  <a href="group__clk__wiz__v1__0.html#gab9224e9f271c5ab6f75811dc297c10db">More...</a><br /></td></tr>
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<tr class="memitem:ga4e61a8e24258a5c6eed44bb975b681a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__clk__wiz__v1__0.html#ga4e61a8e24258a5c6eed44bb975b681a6">XCLK_WIZ_IER_CLK0_MAXFREQ_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga4e61a8e24258a5c6eed44bb975b681a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for User clock 0 max.  <a href="group__clk__wiz__v1__0.html#ga4e61a8e24258a5c6eed44bb975b681a6">More...</a><br /></td></tr>
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